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Virtex® UltraScale+™ 器件FPGA

信息来源 : 网络 | 发布时间 : 2015-04-20 12:00 | 浏览次数 : 3613

业界领先的性能功耗比
Virtex® UltraScale+™ 器件不仅提供 3X 的系统性能功耗比,而且还提供了支持广泛应用的系统集成度和带宽,可充分满足 1+ Tb/s 有线通信、高性能计算以及雷达应用波形处理等需求。 Virtex UltraScale+ 系列可在性能、带宽以及更低时延方面实现一步功能提升,可充分满足要求大规模数据流以及数据包处理的系统需求。Virtex UltraScale+ 器件建立在UltraScale™ 架构的 ASIC-class 优势基础之上,专门针对 Vivado® Design Suite进行了协同优化,可充分发挥 UltraFAST™设计方法优势,加速产品上市进程。

系列包括:

TSMC 的 16FinFET+ 工艺技术可显著提高性能功耗比
UltraRAM 可将片上存储器密度提高 8 倍,从而可提供最低的功耗、最大的灵活性以及最高的可预测性能
PCI Express® Gen 3x16 和 Gen 4x8 集成块支持高带宽接口要求
virtex-ultrascale+
值 特性
可编程的系统集成 
超过 400 Mb 的 UltraRAM 片上存储器集成
集成型 100G 以太网 MAC 以及 RS-FEC 和 150GInterlaken 内核
适用于 PCI Express Gen 3x16 与 Gen 4x8 的集成块
提升的系统性能 
高利用率使速度提升四个等级
高达 128-33G 的收发器可实现 7 Tb 的串行带宽
中间档速率等级芯片可支持 2,666 Mb/s DDR4
BOM 成本削减 
1 Tb MuxSAR 转发器卡减少比例为 5:1
适用于片上存储器集成的 UltraRAM
VCXO 与 fPLL (分频锁相环) 的集成可降低时钟组件成本
总功耗削减 
与 7 系列 FPGA 相比,功耗锐降 60%
电压缩放选项支持高性能与低功耗
紧密型逻辑单元封装减小动态功耗
加速设计生产力 
从 20nm 平面到 16nm FinFET 的无缝引脚迁移+
与 Vivado 设计套件协同优化,加快设计收敛
适用于智能 IP 集成的 SmartConnect 技术


Notes:
1. Relative to the effective logic utilization demonstrated in the competition’s 20nm product portfolio.
2. For full part number details, see the Ordering Information section in DS890, UltraScale Architecture and Product Overview.
3. The B784 package is only offered in 0.8mm ball pitch. All other packages are 1.0mm ball pitch.
 
Disclaimer: This document contains preliminary information and is subject to change without notice. Information provided herein relates to products and/or services not yet available for sale, and provided solely for information purposes and are not intended,
or to be construed, as an offer for sale or an attempted commercialization of the products and/or services referred to herein. Please contact your Xilinx representative for the latest information.
 
 
 General-Purpose Devices Signal Processing Optimized Devices
 Device Name KU3P KU7P KU11P KU15P KU5P KU9P KU13P
Logic
Effective LEs(1)
 (K) 245 485 630 1,100 455 570 715
Logic Cells (K) 205 403 523 915 380 477 597
CLB Flip-Flops (K) 234 461 597 1,045 434 548 683
CLB LUTs (K) 117 230 299 523 217 274 341
Memory
Max. Distributed RAM (Mb) 3.6 6.2 8.9 9.6 6.3 8.8 11.0
Total Block RAM (Mb) 5.1 11.0 21.1 34.6 16.9 32.1 26.2
 UltraRAM (Mb) 18.0 27.0 22.5 36.0 18.0 0 31.5
Integrated
IP
 
DSP Slices 1,056 1,728 2,928 1,968 1,824 2,520 3,528
Video Codec Unit 1 1 0 0 0 0 0
PCIe® Gen3 x16 / Gen4 x8 2 2 4 5 1 0 0
150G Interlaken 0 0 2 4 0 0 0
100G Ethernet w/RS-FEC 0 0 1 4 0 0 0
I/O
Max. Single-Ended HD I/Os 96 96 96 96 72 96 96
Max. Single-Ended HP I/Os 208 416 416 572 208 208 208
GTH 16.3Gb/s Transceivers 16 24 32 44 0 28 28
GTY 32.75Gb/s Transceivers 0 0 20 32 16 0 0
 
Footprint(2)
 
Dimensions
(mm)
HD I/O, HP I/O, GTH 16.3Gb/s, GTY 32.75Gb/s
 
 
 
 
 Packaging
 
 
 
 
 
 B784(3)
23x23 96, 208, 16, 0
C676 27x27 96, 208, 16, 0 96, 208, 16, 0
D676 27x27 72, 208, 0, 16
D900 31x31 96, 312, 16, 0 96, 312, 16, 0
E900 31x31 96, 208, 28, 0 96, 208, 28, 0
D1156 35x35 96, 416, 16, 0 96, 520, 16, 0
E1156 35x35 96, 416, 24, 0 96, 416, 24, 0
E1517 40x40 96, 416, 32, 20 96, 416, 32, 24
E1760 42.5x42.5 96, 572, 32, 24
F1760 42.5x42.5 96, 416, 44, 32 © Copyright 2015 Xilinx
.
Disclaimer: This document contains preliminary information and is subject to change without notice. Information provided herein relates to products and/or services not yet available for sale, and provided solely for information purposes and are not intended,
or to be construed, as an offer for sale or an attempted commercialization of the products and/or services referred to herein. Please contact your Xilinx representative for the latest information.
 
 Page 2
Virtex® UltraScale+™ FPGAs
 Device Name VU3P VU5P VU7P VU9P VU11P VU13P
Logic
Effective LEs(1)
 (K) 830 1,260 1,655 2,485 2,575 3,435
Logic Cells (K) 690 1,051 1,379 2,069 2,147 2,863
CLB Flip-Flops (K) 788 1,201 1,576 2,364 2,454 3,272
CLB LUTs (K) 394 601 788 1,182 1,227 1,636
Memory
Max. Distributed RAM (Mb) 12.1 18.4 24.1 36.1 34.8 46.4
Total Block RAM (Mb) 25.3 36.0 50.6 75.9 70.9 94.5
 UltraRAM (Mb) 90.0 132.2 180.0 270.0 324.0 432.0
Integrated
IP
DSP Slices 2,280 3,474 4,560 6,840 8,928 11,904
PCIe® Gen3 x16 / Gen4 x8 2 4 4 6 3 4
150G Interlaken 3 4 6 9 9 12
100G Ethernet w/ RS-FEC 3 4 6 9 6 8
I/O
Max. Single-Ended HP I/Os 520 832 832 832 624 832
GTY 32.75Gb/s Transceivers 40 80 80 120 96 128
 
 Footprint(2,3)
 Dimensions
(mm)
HP I/O, GTY 32.75Gb/s
Footprint
Compatible
with 20 nm
UltraScale
Devices
C1517 40x40 520, 40
A2104
47.5x47.5 832, 52 832, 52 832, 52
 52.5x52.5(4)
 832, 52
B2104
47.5x47.5 702, 76 702, 76 702, 76 624, 76
 52.5x52.5(4)
 702, 76
C2104
47.5x47.5 416, 80 416, 80 416, 104 416, 96
 52.5x52.5(4)
 416, 104
A2577 52.5x52.5 448, 120 448, 96 448, 128
Notes:
1. Relative to the effective logic utilization demonstrated in the competition’s 20nm product portfolio.
2. For full part number details, see the Ordering Information section in DS890, UltraScale Architecture and Product Overview.
3. All packages are 1.0mm ball pitch.
4. These 52.5x52.5mm packages have the same PCB ball footprint as the 47.5x47.5mm packages and are footprint compatible.
 
 © Copyright 2015 Xilinx
.
Page 3
UltraScale+ Device Ordering Information
 
 
E = Extended (Tj = 0°C to +100°C)
I = Industrial (Tj = –40°C to +100°C)
Important: Verify all data in this document with the device data sheets found at For valid part/package combinations,
go to DS890, UltraScale Architecture and Product Overview: Device-Package Combinations and Maximum I/Os Tables

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